CAREERS
WHY WORK WITH HISOL
People join HISOL because our culture strictly upholds and fulfils employee needs.Hisol offers an attractive and unique opportunity to be part of an exceptional team. We’re also committed to fostering the best possible work environment for our people.
We are always seeking smart and innovative people with strong problem-solving skills. We’re more than just a company. From one project to the next, each day is a new experience. We’re growing rapidly and looking for talented, enthusiastic people to join our team and take on the world’s biggest challenges. To grow, we need people who are innovators and problem solvers.
At Hisol, we believe that its employees and their commitment to excellence have been a major factor in its success and is vital to its continued success.
- Develop test patterns to qualify design rules for correct implementations.
- Develop automation to run regressions, auto detect issues and generate validation reports.
- You are also expected to file bug reports and work closely with runset developers and rule writers on validating the rules.
- Work closely with Technology development on providing feedback on rule wording and correctness.
- Partner with rules owners to ensure clarity and accuracy of rules.
- Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
- Work Experience in Synthesis Constraints development, LINT checks, CDC checks.
- Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure.
- Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.
- Chip-level constraint development and constraint validation.
- Strong knowledge of clock tree synthesis, SI analysis.
- Strong understanding of ECO cycle.
- The layout designer will be responsible for physical design of RF and analog circuits in a fast-paced environment.
- Detail custom layout including floorplan, placement, routing, verification, and release of final database for high frequency RF circuits.
- Has to Provide accurate schedule and plan to meet project milestone deadlines, debug complex verification errors, mentor junior layout designers, able to lead a team to deliver high quality layout that meets design requirements, understanding of hierarchical planning and integration, chip design from top down and bottom up through Tapeout.
- The layout designer should have strong analog layout fundamentals and focused exposure to handling multi voltage domain circuit layouts, latchup and ESD aware layout development strategy.
- Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
- Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
- Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change
- Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow
- Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing
- Supports complex projects or leads smaller independent design activities
- Completes multiple design cycles of moderate complexity with little supervision
- Contributes to PD architecture/Plug-In Unit at the unit level
- As a Verification engineer Working on full chip Verification and UVM Methodology.
- System Verilog is a must.
- Worked on passing test cases, test benches, Building environment.
- Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints
- Good communication skills.
- Expertise in SV-UVM, Coverage Closure, RTL debug till root causing, Low Power Verification/UPF, GLS, Assertions based verification, DPI, Testbench building.
- Familiarity with bus protocols like AHB, AXI, ARM based system architecture, emulation (ex: Veloce), Scripting language like perl
- Excellent problem solving skills and strong communication and team work skills are mandatory
- Formal Verification concepts and working knowledge, C/C++, working knowledge on camera are plus
- Generation of structural ATPG test patterns
- Define and develop scripts for automatic scan insertion
- Generate test patterns and simulate with and without timing annotation
- Debug test failures on silicon products in support of Release to Production
- Working closely with IC Design during test plan and DFT definition, pre-silicon verification(chip level verification) and post silicon validation
- Work closely with IP test development team defining test schemes and implementation styles
- Will assist with silicon debug in the event of yield limiting issues or returned materials
- Working with Product Engineer to address Yield, Design & Quality issues during New Product Introduction phase and to address any post production issues
- Defining scalable pattern methodologies to efficiently test highly configurable embedded SERDES, DDR Interfaces and DAC/ADC hardware
- Defining DFT requirements for next generation products to improve test coverage or time
- Perform the block level and transistor level layout design and optimization of sensor array readout circuits using CAD tools like Cadence Virtuoso and Calibre
- Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors and successfully bring new products from inital concept through release
- New circuit R&D to be ahead of current technology
- Instruct junior engineers when necessary
- Instruct less experienced engineers when necessary
- Designs and tests analog electronic circuits, including sensor interfaces, data converters, multiplexers, active and passive filters, and power distribution systems
- Simulates analog or mixed-signal circuits to ensure that performance, noise, timing, and power requirements are satisfied including worst-case and/or statistical design verification and de-rating analysis
- Designs with unique or leading edge technology, hardware, equipment, or systems to meet or exceed customer requirements
- Generates and reviews development and design approaches for adequacy, feasibility, cost, and conformance to overall goals and best engineering practices
- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)
- Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals
- Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts
- Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)
- Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team
- handle Verilog RTL logic design and debug
- Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation
- Contribute as a design engineer developing the next-generation of multi-core processors
- Specify, design, and synthesize RTL blocks, optimize and floor plan them
- Work with verification engineers to ensure their accuracy