RTL DESIGN
HISOL RTL design engineers have in-depth experience in various aspects of the RTL design flow on chips used in the networking, processors, multimedia, mobile and automotive industries.
Our team possesses how to balance current design techniques with standard IPs and with varying experience ranging from 2 to 10 years on designs going up to multi-million gates. As a result, HISOL earned a reputation in the Semiconductor Industry as the leading RTL design services provider for highly complex designs.
Our Design Engineers coordinate with the architecture team to define micro-architectures for various blocks of DSP core and develop RTL for multiple logic blocks of a DSP core and sub-system for SoC integration. It can run in several frontend tools to check for linting, clock domain crossing.
The RTL Design Engineers work with the physical design team on design constraints and timing closure, work with the low power team on power optimization and coordinate with the verification team to collaborate on test plan, coverage plan, and coverage closure.
OUR RTL DESIGN EXPERTISE
- IP/SoC Design and Verification
- Micro architecture development
- Using different verification methodologies like eRM/OVM/UVM to develop an extendable test-bench/test-cases environment
- Execution of detailed verification plan from spec and working with designers, system engineers, and architects
- Development of verification test bench components for chip/module level using Verilog/System Verilog/C/C++
- Development of BFMs, Monitors, Checkers Blocks level, Sub-system level, and SoC-level verification and Test Bench Development